NAND is an industry "cursed by technology": As Dolphin Research noted in its previous article, "NAND's Innate 'Productivity' and How SanDisk Maintains an 80% Gross Margin," NAND before the AI boom was a typical commodity business—capacity was ruthlessly cleared by the market, technological leadership brought no premiums, only the ability to "lose less than others," with growth dividends entirely consumed by price cuts.

The root cause lies in overproduction on the supply side: By stacking vertically and shrinking horizontally on a single wafer—from BiCS5 to BiCS11 across five generations—SanDisk increased bit output per wafer by 54% per generation, with an annualized compound growth of ~27%.

This means that even without a cent spent on capacity expansion (CapEx), bit capacity automatically swells by nearly 30% annually. The 3D transition period saw a one-time surge, with supply far exceeding demand, making the "asset-light" NAND business even more brutal in downturns than the "asset-heavy" DRAM sector.

The AI boom, however, is rewriting NAND's playbook. In this report, Dolphin Research focuses on how the AI wave has structurally reshaped downstream NAND demand.

Here's a detailed analysis:

1. How has the AI wave structurally reshaped downstream NAND demand?

In the pre-AI consumer electronics cycle, dominant demand drivers—smartphones, PCs, and traditional servers—grew predictably, lacking explosive variables. Thus, cyclical volatility was primarily driven by disorderly supply-side expansion and contraction.

Demand growth came from three drivers: per-device capacity upgrades, penetration into emerging markets, and SSDs replacing HDDs—a gradual yet steady process.

Stable demand paired with rigid supply growth trapped NAND in the classic "silicon cycle": Oversupply → price collapse → manufacturers cut production → low prices stimulate capacity upgrades → rebalancing → price recovery → manufacturers chase high-profit expansion → repeat oversupply.

As long as NAND remained a "peripheral component," this deadlock persisted. The only escape was a new scenario less sensitive to price and directly tied to GPU compute deployment—a role later filled by the AI wave.

Phase Two (Post-2025): AI Inference-Driven Structural Boom

2026 marks NAND's most iconic inflection point: Data centers' share of total NAND demand jumps from ~30% in 2025 to ~45% in 2026, historically surpassing smartphones (which contract to ~23%) to become the largest end market.

The primary driver of NAND demand shifts from price-sensitive, inventory-volatile consumer electronics to cloud providers making decisions based on TCO (Total Cost of Ownership) and ROI (Return on Investment), becoming price-insensitive.

Cloud vendors no longer ask, "Are chips cheap this quarter?" but rather, "Can we secure sufficient high-performance eSSDs on time to support GPU infrastructure for the next three years?" The shift from "short-term price pressure" to "long-term supply guarantees" underpins manufacturers' adoption of NBM (New Binding Mode contracts).

Accompanying this market base shift and AI's "training-to-inference" transition, NAND's role fundamentally changes:

In early AI, NAND served as a peripheral "data warehouse": Static training data, model weights, and crash-proof checkpoints were stored near GPUs for quick retrieval. This data was highly replaceable—re-downloadable from data lakes at minimal bandwidth and electricity costs, avoiding expensive GPU recomputation.

In the inference era, computing becomes high-concurrency, continuous "dynamic consumption"—storage demand scales with "AI users × usage frequency × context length." Critically, NAND now stores "intermediate computational products" for the first time.

The massive KV Cache generated by long-text inference isn't static data imported externally—it's GPU-generated "working memory" consuming significant compute. If lost, no central backup exists, requiring expensive GPU recomputation and electricity.

Storage value now directly translates to "compute and electricity savings." As SanDisk notes, SSDs have evolved into "Token batteries": Tokens represent work already done—better to "charge" them into drives than discard and recompute, saving cloud providers power and compute.

Kioxia's forecast confirms this trend: Total data center NAND demand will surge from 286 EB in 2025 to 1,686 EB in 2031 (CAGR 34%), with extreme internal differentiation:

AI Inference: Skyrockets from 86 EB in 2025 to 1,251 EB in 2031 (CAGR 56%), accounting for 74% of data center NAND demand by 2031.

AI Training & Traditional Workloads: AI training grows at just 11% CAGR, while traditional CPU-driven cloud workloads grow at 14%.

Inference demand grows 5x faster than training—this NAND supercycle will be primarily driven by inference.

Key NAND Applications in AI Data Centers:

① KV Cache Offloading—NAND as GPU's Context Storage Layer

During AI inference, GPUs must compute and maintain KV Cache (the model's "working memory") for each token in real time. Early architectures treated it as disposable: After a conversation ended or GPU VRAM needed to serve another user, HBM-stored KV Cache was cleared.

When users asked follow-ups or multiple users concurrently accessed the same ultra-long document, systems had to re-feed contexts to GPUs for expensive recomputation (Prefill).

Prefill is inference's first step: GPUs read all inputs at once, calculate token relationships (Attention mechanism), and regenerate KV Cache—the most compute- and power-intensive phase.

Previously, "use-and-discard" made sense for two reasons:

a. Recomputation was cheaper than storage: In early models (e.g., GPT-3) with 2K-token contexts, KV Cache was small—GPUs could recompute it in <1 second. Storing it required CPU/memory transfers and PCIe latency, sometimes taking longer than recomputation.

b. HBM was scarce and expensive: GPU VRAM was precious, reserved for active computational tasks, not long-term storage of inactive user histories.

The long-text era upends this logic: From GPT-3's 2K tokens in 2020 to million-token contexts in 2026 mainstream models, a 500x surge. Recomputing million-token KV Cache requires expensive GPUs to run at full load for seconds, incurring compute and electricity costs.

This redefines KV Cache: NVIDIA's ICMS (Inference Context Memory Storage) architecture formally classifies it as "AI-native persistent data," not disposable cache.

Now that temporary cache becomes persistent, does the math work?

a. Capacity Constraints: Algorithmic compression can't keep pace with KV Cache growth

The first condition is that HBM expansion lags far behind KV Cache growth.

Total KV Cache = Context Length × Concurrent Sessions × Per-Token Storage. Currently, the first two variables explode:

Context lengths double annually: Mainstream models evolve from 4K→128K→1M+, linearly scaling KV Cache.

Concurrency and inference rounds surge—driven by three architectures:

a. RAG (Retrieval-Augmented Generation): A single query may ingest two books. Systems concatenate retrieved documents into inputs, sending far more tokens to GPUs than the original question, blowing up KV Cache.

b. Agentic Search: AI shifts from "question-answer" to autonomous "plan-execute-evaluate-retrieve" loops. Multi-step tasks expand single-task token consumption from hundreds to millions.

c. Multi-Agent: Concurrent collaboration among agents multiplies KV Cache storage needs.

Model vendors double context lengths annually, but HBM physical expansion nears limits: Single-card capacity doubles every 2-3 years, with slowing returns.

To assess KV Cache overflow, consider available HBM per inference rack. Take Rubin NVL72's 21TB HBM:

Deploying a 2.8T-parameter flagship MoE model (FP8) uses ~2.8TB for weights; subtracting activations, paging, and framework overhead (~12%, ~2.5TB) leaves ~15.4TB for KV Cache.

Uncompressed, 100K tokens occupy ~40GB. Even with cutting-edge compression (e.g., Google TurboQuant, 16-bit→3-bit, ~5-6x lossless), 1M tokens require 67-80GB.

Thus, a $5M rack can serve just 193-230 concurrent million-token sessions—extremely low ROI for enterprise cloud services.

Once contexts hit 5M tokens or concurrency breaches this threshold, rack-level HBM pools saturate rapidly. Offloading KV Cache from HBM → DRAM → NAND becomes inevitable.

b. Low cost, a fatal attraction

Even if the HBM capacity is barely sufficient, it is not economically viable to use it for long-term retention of KV Cache: HBM4 costs approximately $16/GB, while eSSD costs around $0.3-0.4/GB, making the former 40-50 times more expensive than the latter. Using it to store 'warm/cold KV Cache' that is rarely accessed over hours represents a severe misallocation of resources.

To address this, NVIDIA has established a new tiered memory architecture: G1 HBM → G2 system DRAM → G3 local SSD (NAND) → G4 shared network storage (NAND/HDD), orchestrated at the software layer by NVIDIA Dynamo to enable transparent migration of KV Cache across these tiers.

NVIDIA estimates that each GPU module may require up to 16 TB of KV Cache for large-scale multi-agent inference. Therefore, the Rubin platform incorporates an ICMS/CMX contextual storage layer between G3 local SSD and G4 shared storage, defined as G3.5—since G3 has limited capacity and cannot be shared across nodes, it cannot support large-scale reuse in multi-agent scenarios.

The CMX single-layer capacity is approximately 16 TB, nearly 60 times that of a single card's 288 GB HBM—only with the affordability of NAND can such large-scale storage be economically feasible.

c. Switching to NAND: Can latency keep up?

The viability of offloading ultimately depends on TTFT (Time To First Token) latency—only if the time and cost of 'reading back from SSD' are lower than 'recomputing with GPU' does offloading make commercial sense.

GPU Direct Storage (GDS) is key to overcoming this barrier: it bypasses the CPU and DRAM, establishing a direct high-speed pathway via PCIe/RDMA between eSSD and GPU memory.

Publicly verified tests show that GDS, combined with compression technology, can improve KV Cache restoration latency by 10x, making ultra-low-latency contextual delivery engineeringly feasible.

NAND-stored KV Cache data types: 'shared memory' and high-frequency reuse

Even after overcoming capacity and cost barriers, offloading KV Cache to NAND requires two conditions:

Condition 1: Must be shared cache

a. Ephemeral cache (word-by-word generated drafts): HBM-hosted

When AI responds word-by-word (Decode phase), it must reread the entire historical context for each token generated. Forcing writes to SSD at this stage would: (1) fail to keep pace with AI's speech rhythm due to insufficient bandwidth (speed wall), and (2) exhaust enterprise-grade HDD lifespan within weeks through high-frequency fragmented writes (endurance wall). Thus, such drafts must remain in HBM memory and are prohibited from disk storage.

b. Shared cache (statically packaged records): NAND-stored

Only when AI completes reading ultra-long prompts (Prefill phase), users switch conversations, or Agents suspend tasks does fully computed, segment-packable complete context emerge. This data is 'large-block, sequential, and low-frequency,' resembling archival box transfers of finalized documents—perfectly matching NAND's large-block sequential read/write characteristics. Only such data qualifies for NAND-tier storage.

Condition 2: High-frequency reuse to 'justify the cost'

Beyond technical feasibility, economic viability matters: Offloading net benefit = Reuse frequency × (Recomputation cost - Readback cost) - (Write cost + Storage occupancy cost)

GPU recomputation consumes both power and compute resources. Reading precomputed cache from SSD becomes cost-neutral after just 1-2 reuses. The challenge lies in scarce disk space—only highly reused contexts justify storage allocation.

This distills to a core metric: cache hit rate. Higher hit rates drive marginal service costs toward zero. For new requests, the system retrieves backups from disk via 'prefix matching,' skipping costly Prefill recomputation.

As the Manus team notes: Cached tokens cost ~10x less than uncached ones. Typical large models achieve 40%-70% hit rates (MiniMax 71%, Z.ai GLM5 ~40%), while multi-step Agent scenarios consistently exceed 95% (DeepSeek measured 98.7%), realizing 'write once, read thousands of times' efficiency.

In practice, conversation elongation or GPU user switches free HBM space for current KV Cache. If sessions require reuse, they can be stored in NAND and reloaded upon service resumption.

Typical offloading scenarios include: user reading pauses, cross-period historical retrieval, Agent suspension gaps, ultra-large-scale concurrent sharing, and enterprise knowledge base calls.

KV Cache tiering: AI inference's storage demand spans from high-performance flash (pSLC/TLC) to massive warm/cold storage (QLC), pulling the entire enterprise storage product line—including DRAM and HBM—upward.

Along this spectrum, storage types have clear roles:

DRAM (G2) handles 'hot overflow' from active tasks: As HBM's direct buffer, it accommodates KV data exceeding video memory limits during active sessions. Fast speeds prevent conversation stuttering, but data is lost on power failure.

NAND (G3–G4) dominates 'persistent reuse' of high-value assets: After crossing the power-loss retention threshold, data enters non-volatile flash-based persistent reuse chains, sinking tier-by-tier according to media characteristics:

a. G3 direct-attach layer (pSLC/performance TLC): Hosts recently offloaded, frequently reactivated warm session contexts.

b. G3.5 local network layer (endurance TLC): Stores System Prompts and Agent states requiring cross-node high-frequency sharing within the same compute cluster.

c. G4 remote archive layer (high-capacity QLC/HDD): Holds massive, extremely infrequently accessed RAG enterprise knowledge bases and historical conversation archives.

② Staging scenarios: TLC and pSLC as rigid foundations

SanDisk estimates Staging (data staged for immediate HBM access, akin to backstage waiting) will account for 40% of AI datacenter NAND demand by 2030—the largest single segment, entirely served by TLC (including pSLC).

Analogy: Data retrieved from data lakes first resides in high-speed NVMe SSD buffers (G3 direct-attach SSD) adjacent to GPU motherboards—like a chef's cutting board beside prep stations. Ingredients needn't be fetched from cold storage for every chop.

a. Training-side Staging: Burst overwrite

Core tasks include model 'checkpoints' (periodic saves) and dataset staging. Training trillion-parameter models generates TB-scale archives every few dozen minutes.

While modern techniques enable asynchronous 'compute-while-saving' (avoiding idle GPU waits), such massive concurrent disk writes still severely contend for bandwidth. Prolonged checkpointing increasingly disrupts compute pipelines.

Thus, training-side Staging faces dual constraints: withstanding repeated overwrite wear while minimizing write windows.

b. Inference-side Staging: High-concurrency reads

Three key inference-side Staging tasks share read-intensive, write-rare characteristics:

Model cold starts and elastic scaling: Training machines run continuously, but inference machines must frequently scale capacity and power cycle with traffic peaks. Since memory is volatile, new nodes rely on local SSDs' high sequential read bandwidth to instantly load parameters into empty video memory ('second-level readiness'), potentially triggering dozens of daily reloads.

Multi-model/multi-version dynamic residency: Production nodes often serve 'full suites' (multiple sizes, precisions, versions) totaling tens of TB. Single-card video memory (288GB) and system memory fall 1-2 orders of magnitude short—only 4-16TB direct-attach SSDs can accommodate complete toolkits. Letting rarely used old models occupy expensive video memory is inefficient; SSD-based swapping is optimal.

Facing such extreme I/O intensity, media types are progressively eliminated:

HBM & DRAM: Prohibitively expensive and capacity-constrained, reserved for active KV Cache. DRAM's volatility is fatal—checkpoints exist precisely for post-crash recovery.

HDD: Throughput cannot match GPU's burst large-block writes, and physical constraints prevent installation in GPU compute tray cabinets.

QLC: Endurance is ~1/10th of TLC's (QLC ~1,000 cycles vs. TLC ~10,000 cycles). Staging represents AI storage's most write-intensive layer—QLC would rapidly exhaust lifespan. This is a hard constraint, not cost tradeoff.

Thus, TLC fits Staging, but falls short in some scenarios, necessitating pSLC:

pSLC repurposes TLC or QLC cells as SLC—storing 1 bit per cell instead of 3-4 bits. This trades ~2/3rds effective capacity for longer endurance and lower write latency.

The direct consequence: Achieving standard SSD capacity requires 3-4x wafer output. Core trigger scenarios include high-frequency vector retrieval for RAG and Agentic Search.

New characteristics of large-scale AI agent vector retrieval (below) compel NAND to operate in high-speed pSLC mode:

a. Excessively fragmented access (ultra-fine granularity): AI knowledge base searches often compare tiny feature strings (hundreds of bytes). Standard TLC SSDs must read entire 4KB pages even for single-byte requests, wasting bandwidth.

b. Extremely dense concurrency: Modern AI plans, tools, and iteratively queries—single tasks moment split into thousands of concurrent 'dictionary lookups.' Standard TLC SSDs saturate under such loads.

c. Simultaneous read/write pressure: AI agents update indexes and record intermediate states while querying. This 'reading while note-taking' intensity rapidly exhausts ordinary TLC lifespan, while pSLC endures 10x longer.

However, the next-generation direct-connect architecture hosting this tier—NVIDIA Storage-Next (G2.6 tier, positioned below G2.5 CXL memory and above G3 local SSDs)—remains in the stage where NVIDIA leads specification definition in collaboration with vendors like Kioxia.

Its positioning is to introduce a new pSLC storage tier directly connected to the GPU between DDR and local SSDs, enabling NAND to achieve DRAM-like IOPS and access granularity (512B fine-grained random access) while retaining low-cost, high-capacity advantages.

③ Fast Data Lake Scenario: QLC's Main Battlefield

If GPU-direct SSDs are the "cutting board" beside the prep station requiring dual read-write capabilities, the Fast Data Lake (G4 remote network tier) in AI data centers serves as the "remote central warehouse" focused on reading: storing all assets required for AI operations at petabyte-scale capacity—training corpora, multimodal datasets, model weights across versions, RAG knowledge bases, and inference feedback logs.

Based on SanDisk's 2030 demand breakdown, Fast Data Lake accounts for approximately 25% of NAND demand in AI data centers, almost entirely served by QLC.

The core question is: Can QLC replace HDDs? Dolphin Research believes this requires analysis across multiple dimensions:

a. Hot Data: QLC Dominates

Data being actively consumed by CPUs/GPUs (e.g., processing training sets, RAG knowledge bases awaiting retrieval) demands extremely high data throughput.

HDDs' mechanical head seek latency (millisecond-scale) differs by two orders of magnitude from AI's microsecond-scale requirements, making them physically unsuitable. With its massive capacity and read/write bandwidth, QLC becomes the absolute main force (mainstay) for this tier.

b. Warm/Cold Data: HDDs Retain Primacy

For "archival reference" and "historical backup" data, QLC adoption depends on two dimensions:

① Supply-Side Disruptions: Short-Term "Pseudo-Replacement"

A 300EB–400EB HDD supply gap will emerge in the short term. Some cloud providers currently use eSSDs as temporary solutions, creating an illusion of accelerated replacement.

However, HDDs can also boost production using SSD-like technologies, causing eSSD-covered pure capacity demand to reflow (flow back) to HDDs, weakening the replacement logic.

② Economic Viability: QLC Price Hikes Negate Benefits

While short-term supply shortages drive substitution, subsequent QLC price increases due to hot-data tier demand make it economically unviable. The current per-GB price gap between HDDs and QLC has surged to 20–25x. For warm/cold data storage, QLC struggles to displace HDDs unless large-capacity, low-cost QLC products emerge.

Thus, QLC's replacement of HDDs follows three distinct narratives:

a. On performance-critical paths (hot data), replacement is complete and irreversible;

b. For warm/cold archival tiers, high price differentials block normal substitution, with current "replacement shares" driven by HDD shortages serving as temporary stopgaps facing future reflow (reversion) risks;

c. Long-term success hinges on mass production of high-capacity, high-density QLC, which must achieve sufficient "space and energy compression" to cross the 2-3x TCO replacement threshold.

According to SanDisk's earnings call, ultra-high-capacity QLC generated its first revenue in FQ4'26 (April-June 2026), with early ramp-up starting in FQ1'27. SanDisk expects QLC's share of total bit shipments to rise from ~20% in 2025 to 40% by FY2026 end, driven by Stargate (ultra-high-capacity QLC) adoption by cloud providers.

④ HBF: Demand Upside Option

In traditional AI storage hierarchies, HBM adjacent to GPUs offers nanosecond-scale latency and ultra-high bandwidth but suffers from small per-stack capacity and high costs due to DRAM process limitations. Moving down to NVMe SSDs introduces severe latency/bandwidth gaps.

NAND vendors are now promoting HBF (High Bandwidth Flash)—essentially a replica of HBM's architecture: multi-layer stacking, TSV vertical interconnects, and co-packaging with XPUs, but replacing DRAM dies with NAND dies.

SanDisk's developing HBF claims 16-layer NAND stacking, delivering 8x capacity at HBM-class bandwidth levels. (Reference: From HBM height limits to NAND scaling—who controls whom between NVIDIA and storage capacity?).

HBF and HBM represent complementary strengths rather than direct substitution:

HBF excels in capacity and cost but suffers from microsecond-scale latency, making it slow for fragmented random reads, and has physical endurance limits, restricting it to "read-only reference" roles unsuitable for high-frequency writes.

Additionally, HBF remains in engineering development: pilot production lines launch in H2 2026, with commercialization expected in 2027, but thermal standards for deployment adjacent to high-heat GPUs remain undefined.

This creates a functional division:

HBM focuses on "performance first," becoming mandatory for flagship GPUs to handle latency-sensitive prefetch stages, high-frequency KV Cache operations, and training tasks requiring symmetric read/write bandwidth.

HBF prioritizes "capacity first," managing sequential-read-heavy regular inference, long-text and MoE scenarios requiring full model storage on single machines, and read-dominated warm/cold KV Cache offloading, enabling mid-range GPUs and future edge devices to run ultra-large models.

Dolphin Research believes HBF will coexist with rather than disrupt HBM—HBM manages latency-sensitive hot data, while HBF handles capacity-hungry warm data. Future HBF penetration requires continued observation.

SanDisk categorizes HBF into four deployment models (details in "AI Inference Boom: Can SanDisk Rise from the Ashes?"). Dolphin Research considers ③ Hybrid (HBF+HBM) and ④ Disaggregated (pooled) models most likely to materialize.

The hybrid logic is straightforward: HBM remains, with HBF added alongside. GPU vendors avoid major redesigns—HBM handles its strengths while HBF stores weights and cold KV Cache. SK Hynix's new H3 architecture exemplifies this HBM+HBF hybrid approach, with mass production in 2027 and customer adoption in 2028 representing the path of least resistance.

The disaggregated model separates HBF from GPUs, deploying it in pool-like configurations connected via networks, similar to NVIDIA's CMX rack-scale storage pool concept. However, this requires network architecture upgrades and may only become practical post-2028.

From vendor roadmaps, HBF remains in standard alliance phase, not yet incorporated into GPU vendors' (especially NVIDIA's) official architectural standards.

SanDisk and SK Hynix are currently the sole substantive promoters: they formed a standard alliance and established pilot lines in early 2026, half a year ahead of schedule, with chip production expected by end-2026, controller launch in 2027, and mass production targeted for 2027.

Google, NVIDIA, and AMD may adopt HBF as customers only by 2028 at earliest, but adoption ≠ definition—HBF's full integration into GPU architectures requires standard certification, reference design integration, and ecosystem adaptation.

Other vendors: Samsung holds patents but hasn't disclosed prototypes or timelines; Kioxia pursues XL-FLASH (G2.6 Storage Next), not directly competing with HBF; Micron lacks public plans.

Overall, while HBF's industrialization timeline accelerates, the landscape remains "storage vendors driving, GPU vendors not yet onboard." True differentiation awaits 2027 sample performance and 2028 head customer system design inclusions.

Summary:

AI's transformation of NAND demand doesn't merely elevate the demand curve—it offers hope to break the "silicon cycle" curse: Under "compute deployment and inference workload dominance," NAND evolves from a "peripheral component" to a "computational path necessity."

In the "training-to-inference" and long-context era, storing KV Cache in NAND preserves expensive GPU compute and electricity resources, making SSDs effectively "token batteries."

SanDisk projects AI data center NAND shipments to reach 1.2 ZB by 2030 (tripling from 2026), with three core workloads clearly defined:

a. Staging Tier (40%): Ultra-high-intensity I/O buffer adjacent to GPUs, dominated by high-performance TLC (and pSLC) due to extreme write endurance and concurrency demands.

b. KV Cache Offloading Tier (35%): Entirely new inference-era demand, absorbing HBM overflow capacity through TLC/QLC tiering.

c. Fast Data Lake (25%): Remote central data repository, firmly served by high-capacity QLC.

By NAND type, TLC accounts for 66% and QLC 34%: The dominant Staging tier naturally rejects QLC due to write intensity, securing TLC's base; QLC focuses on data lakes and warm/cold KV Cache offloading.

These workloads evolve in opposite directions: Data lakes pursue "cheaper" QLC capacity scaling, while Staging and hot paths demand "faster, more durable" TLC/pSLC (sacrificing ~2/3 capacity for 10x endurance).

How long can this pricing supercycle last? At current valuations, does reborn SanDisk still have upside? Dolphin Research will analyze this in the next installment—stay tuned!

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