The chain reactions set off by large-scale delivery are already rippling across the industry chain.

Not long ago, Jensen Huang took the stage at GTC Berlin, a massive LED screen behind him displaying a rendering of the Vera Rubin rack.

He unveiled something called DSX POD—a modular AI factory reference design in which computing, networking, cabling and liquid-cooling piping are all pre-installed at partners' factories, shipped to the customer site, hooked up to power and cooling, and up and running within 14 days. Previously, that cycle was measured in half-years.

Over the past two years, the computing-power demands of large-model training have undergone a quiet but thorough shift. The experience of the hundreds-of-billions-parameter era was "add cards": if one isn't enough, add eight; if eight aren't enough, add a cluster. But as parameter scales move toward trillions and the MoE architecture becomes mainstream, the losses from cross-node communication are beginning to eat away at the gains from linearly stacking cards.

If a 10,000-card cluster lacks sufficient interconnect efficiency, the computing power it actually delivers may be less than half its nominal value. This is not a chip-performance problem; it is a system problem.

Almost simultaneously, research reports from domestic sell-side analysts came out in quick succession. In a commentary the next day, CITIC Securities offered this judgment: domestic and foreign vendors are releasing super node products intensively, and the super node industry is formally moving from the solution-validation stage into large-scale delivery. Server complete machines, switch chips, connectors and liquid cooling were named one by one.

2026 is expected to be the first year of volume production for domestic super nodes. The weight of this judgment lies not in "another track has kicked off," but in the fact that it marks a dividing line: super nodes moving from engineering prototypes to batch delivery means the competition rules for computing power infrastructure have shifted.

01 From "stacking cards" to "stacking systems": the computing power race has changed tracks

To understand why super nodes are erupting in concentrated fashion at this particular moment, one must first return to an engineering dilemma.

There is an old problem in large-model training called communication overhead. No matter how powerful a single GPU is, it still has to wait to receive data from other cards before it can compute.

The traditional approach is Scale-out, distributing tens of thousands of cards across different servers and connecting them via Ethernet or InfiniBand. This approach scales decently, but cross-node communication latency and bandwidth remain bottlenecks. Tensor parallelism (TP) is extremely sensitive to latency. As parameter scale grows, a large amount of time is spent waiting for data, while the time actually spent computing is compressed.

There is an unpleasant term in the industry called the "computing power idle rate." When traditional clusters run large models, the linear acceleration ratio is often less than 50%—meaning that if you buy 10,000 cards, the actual effect may be equivalent to only a little more than 5,000. The remaining capacity is consumed by cards waiting on one another.

The solution offered by super nodes is Scale-up. Dozens, hundreds, or even thousands of cards are placed in a tightly coupled domain, connected by a high-speed interconnect bus and uniformly addressed.

To upper-layer software, this large pool of cards is like a giant graphics card, with memory directly accessible across cards and communication latency compressed from microseconds to nanoseconds. ZTE used an analogy in its "Super Node Technology White Paper" released this year: "one rack is one giant GPU."

Two driving forces stand behind this shift.

First, changes in model architecture. After MoE (Mixture of Experts) became mainstream, inter-card communication patterns changed from dense full exchange to sparse on-demand routing. The requirement for interconnect bandwidth did not fall but rose, while tolerance for latency became narrower—because the scheduling window for expert routing is very short.

Second, the physical ceiling of single chips. The dividends of advanced processes are narrowing, and the growth curves of memory capacity and bandwidth for a single chip are beginning to fall behind the expansion speed of model parameters. Stitching more cards together with lower latency has become a more realistic engineering path than continuing to shrink transistors.

The Ascend 960 super node released by Huawei at its September all-connect conference this year pushed this idea to a new magnitude. A single super node can scale to 4,096 cards, uses unified memory addressing based on LingQu UnifiedBus, and reaches 8 EFLOPS of FP8 computing power.

More noteworthy is the interconnect solution it uses, the Hi-ONE NPO optical engine, with a total capacity of 7.2T. It uses 5,500 optical engines to replace the 48,000 800G optical modules originally required, reducing power consumption by more than 550 kilowatts. The term NPO (Near-Package Optics) has frequently appeared in various technical releases over the past six months.

Alibaba is not slow either. At the Preheating event of this year's Apsara Conference, T-Head demonstrated the Panjiu AL128, with 128 cards tightly coupled in a single rack, P2P latency below 150 nanoseconds, and single-rack bandwidth reaching the Pb/s level. It is already running on the Bailian platform, carrying model services for Tongyi Qianwen, DeepSeek and Kimi.

By September, the AL64 distributed SNPO optical interconnect super node was released, billed as the world's first product to implement near-package optics dedicated to ScaleUp. The roadmap also includes the AL144, expected in 2028.

Viewed over a longer span, this is not a single-point breakthrough by one company, but a collective turn by the entire industry at the same technological inflection point. This year's "AI Computing Node Development Research Report" from CAICT mentions that the cluster linear acceleration ratio is climbing from a level of less than 50% under traditional architectures toward a range above 88%.

Behind this number is the fact that a dual-layer architecture of Scale-up tight coupling plus Scale-out cross-super-node networking is becoming the new standard.

02 The world of interconnect protocols: whoever defines the rules collects the rent

The competitive barrier of super nodes is not in the chips themselves, but in the interconnect.

This sounds a bit counterintuitive. After all, when people buy AI computing power, their first reaction is to look at the computing power parameters of the GPU/NPU. But what really determines whether a super node is good to use is how wide, how stable and how low-latency the "road" between cards is. And the right to define this road is currently dispersed among several players.

NVIDIA holds NVLink. Starting with GB200 NVL72, NVLink binds 72 GPUs into one rack through orthogonal backplane direct connections. The evolution rhythm of this line is very clear: after NVL72 comes NVL144, NVL288, and further up NVL576. Each generation makes the Scale-up domain larger, and the share of optical interconnect also increases.

The DSX POD released at GTC Berlin essentially packages this system integration capability into a standardized reference design and hands it to partners such as Dell, Supermicro and Quanta for delivery. NVIDIA's role is increasingly like the Intel of computing power—not only selling chips, but also selling reference architectures for entire racks.

Huawei is betting on LingQu. At this year's MWC, the Atlas 950 SuperPoD made its overseas debut, supporting up to 8,192 cards with LingQu interconnect. By the September all-connect conference, the technical details of LingQu were systematically laid out: one set of protocols equally connects all components in the cluster, supports memory access across physical servers, and follows an interconnect strategy of copper for short distances and optics for long distances.

Huawei named this architecture Peerium. Xu Zhijun once mentioned an ambitious formulation on an internal occasion: make a million processors become one computer. Multiple Ascend 960 super nodes can then be networked through LingQu or RoCE, scaling up to 512,000 cards, and with multi-rail topology theoretically reaching a scale of 1 million cards.

Alibaba is taking the route of self-developed interconnect chips. Behind the Panjiu series is a chip called ICN Switch, specifically designed to solve in-rack interconnect problems. The AL128 uses this chip to pack 128 cards into one rack. The AL64 released at the Apsara Conference goes further by introducing SNPO all-optical interconnect, extending optical interconnect from inter-rack to near-package positions within the rack.

Alibaba's approach is somewhat different from Huawei's. It is more like a cloud vendor using system engineering capabilities to absorb the production capacity of self-developed chips. The Panjiu series first serves its own Bailian platform and internal large-model business, and external output is a matter for the next step.

ZTE launched the OEX orthogonal backplane-free interconnect architecture in April. The "backplane-free" idea is somewhat interesting—traditional server racks rely on backplane routing, and as signal rates rise, the loss and crosstalk of the backplane are hard to suppress. ZTE removed the backplane and switched to orthogonal direct connection plus high-speed connectors, claiming zero cables. The 64-card Matrix cluster has already been winning industry awards.

Further down the list, Kunlunxin's super node showed a mass-production version at this year's WAIC, with 32 or 64 cards per rack, scalable to 512 cards, and cold-plate liquid cooling. Baidu, Hygon, MetaX, Moore Threads, Enflame and Biren—almost all leading domestic AI chip companies unveiled their own super node solutions this summer. The "Guangyue 128-card commercial version" jointly developed by Lightelligence and Biren landed in Shanghai this year, using an optical switching route.

The key variable in this competition lies in the degree of openness of the interconnect protocols. NVIDIA's NVLink is relatively closed, with an ecosystem built around CUDA and NVLink-C2C. Huawei is promoting CANN open source and trying to make LingQu an open protocol. Alibaba's ICN Switch currently appears to be mainly for internal use, but if the SNPO optical interconnect technology route is adopted by the industry, it could also become a de facto standard. ZTE's OEX architecture leans more toward complete-rack delivery and is not bound to a specific chip vendor.

Once a company's interconnect protocol can become an industry standard, it may be able to obtain a "rent-collecting" position in the next generation of computing power infrastructure similar to that of PCIe or NVLink in the past. This is a much bigger business than simply selling chips. Because once the protocol is set, switch chips, connectors, PCBs and optical modules all have to be adapted around it.

03 From exhibition stand to machine room: what large-scale delivery means

Over the past two years, super nodes from various companies mostly remained at the stage of launch events and exhibition stands. Huawei's Atlas 950 only made its first appearance in February, Alibaba's AL128 only went online on Bailian in the middle of the year, and Kunlunxin's mass-production version was shown in August. Cases that truly entered customer machine rooms and ran production workloads were few and far between.

The change happened in the most recent quarter.

On NVIDIA's side, mass production of Vera Rubin NVL72 is accelerating. Racks at CoreWeave, Google Cloud, Microsoft Azure and Oracle Cloud are already running, and the supply chain covers more than 350 factories in 30 countries. DSX POD pushes the delivery model one step further: modular container-based pre-integration, going live on site in 14 days, with formal delivery by partners in early 2027.

The timing of this node is very deliberate: Europe has a large AI computing power gap, but customers' ability to build their own machine rooms varies. Prefabricated AI factories precisely hit this pain point.

On the domestic side, CITIC's research report judges that 2026 will be the first year of domestic super node implementation. Leading cloud vendors and industry customers are beginning deployment, and penetration is entering a fast-rising channel.

Huawei's Ascend 960 targets training and inference scenarios for ten-trillion-parameter models, with target customers being operators, national computing power hubs and large industry intelligent computing centers. Alibaba's Panjiu first serves internal demand—dozens of third-party large models are running on the Bailian platform, and the explosive demand for inference computing power directly drove procurement of super nodes.

The chain reactions brought by large-scale delivery have already begun to appear across the industry chain.

The most intuitive change is the delivery unit. In the past, servers were sold by unit, eight cards per machine, and customers bought hundreds of them and networked them themselves. In the super node era, the delivery unit has become the entire rack or even the entire Pod, and computing, switching, power supply and liquid cooling must be co-designed before leaving the factory.

This means the role of server vendors has changed from hardware assemblers to system integrators, and both technical barriers and customer stickiness are moving upward. For complete-machine manufacturers such as Inspur Information, Huaqin Technology and Sugon, the value per device is rising.

Switch chips are another beneficiary. The scale-up architecture introduces an additional layer of in-rack switching, and the ratio of switch chips to AI chips has risen significantly. Furthermore, the specifications for this tier of switching far exceed those of traditional top-of-rack (ToR) switches: bandwidth must keep pace with inter-card interconnect, and latency must be compressed to the nanosecond level. Domestic switch chip maker Centec Networks, along with Ruijie Networks, which produces complete switches, are both capitalizing on this incremental market.

The pace of connector iteration is also accelerating. Orthogonal direct connection and backplane-free architectures have driven growth in the adoption of high-speed connectors, with rates advancing from 56G to 112G and 224G. For manufacturers such as Huafeng Technology that produce high-speed backplane connectors, there is room for product unit prices to rise.

Liquid cooling has become virtually standard for super nodes. Huawei's Ascend 960 employs a full liquid cooling design, Alibaba's Panjiu also uses cold-plate liquid cooling, and Kunlunxin's mass-production version follows suit.

However, super nodes are not a cure-all. They address communication efficiency within the rack and in the near-rack range, but scheduling across machine rooms and regions still must go through the scale-out network. Additionally, super nodes place extremely high demands on the software stack. Unified memory addressing sounds appealing, but upper-layer frameworks, communication libraries, and compilers must all be adapted accordingly.

Domestic vendors also face a practical constraint. Access to advanced processes is limited, and single-chip performance still lags behind NVIDIA. To some extent, super nodes rely on system integration to compensate for shortcomings in single-point performance. Since a single card cannot compete, more cards are stitched together with lower latency to close the gap through system-level efficiency.

Whether this strategy can hold up over the long term depends on where the ceiling of interconnect technology lies. If the scale-up domain expands from 4,096 cards to over ten thousand cards and communication overhead begins to accumulate again, the marginal returns of the entire architecture will diminish.

Super nodes moving toward large-scale delivery means the main battleground of computing power competition has shifted from chip generations to system integration. Excelling in scale-up interconnect translates into shorter delivery cycles, faster customer onboarding, and a larger share in the next round of large-model training infrastructure tenders—this is the common pursuit of all players.

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